Televisions with multiple channel reception capabilities can provide desirable features such as picture-in-picture, recording one or more channels while watching another one, and fast channel switching time between a few adjacent channels or a few recently tuned channels. Typically, multiple tuners are provided to enable these capabilities. In general, these tuners are each implemented as a discrete tuner. While there have been efforts to implement a single tuner in a single semiconductor die integrated circuit (IC), it has proven difficult to incorporate more than one tuner on a single die, particularly in terms of area and power consumption, and performance issues.
Recently, implementation of single-chip multi-tuner solutions has gained interest, as it can be more cost and power efficient compared to multiple single chip tuner solutions. Solutions are typically based on directly digitizing the entire TV spectrum (e.g., 42 MHz to 1 GHz for the cable TV spectrum). These products are called full band capture or full spectrum capture devices. The core of the analog part of such devices is a very high-speed analog-to-digital (ADC) with a sampling clock frequency of 2 GHz-3 GHz that can potentially digitize the entire cable spectrum. A highly linear, typically off-chip, low noise amplifier (LNA) precedes the ADC. The ADC requires about 10-bits of resolution and 60 dB spurious frequency dynamic range (SFDR). In current technologies, design of an ADC that operates at such high bandwidth and dynamic range is quite challenging, therefore some amount of interleaving is typically employed (e.g., 2 to 64 channels). Key signal processing functions such as down conversion and blocker filtering are pushed to the digital domain in the full band capture device. In this way, information of all of the interleaved channels of the ADC is needed to process single desired channel. The processing burden of the digital section is further increased due to inter-channel calibration needs of the time-interleaved ADC.